1. Field
The present disclosure relates to data conversion. In particular, it relates to a switching arrangement and to a digital-to-analog converter (DAC) mismatch shaper using the same.
2. Related Art
Direct data conversion at IF frequencies offers many advantages in transceiver design. By eliminating the IF mixers and filters, the resultant system is smaller and simpler than a traditional IF transceiver architecture. Additionally, by eliminating the 1st-IF upconversion, direct-IF data conversion avoids the noise, linearity, I/Q cancellation and clock feedthrough issues that plague mixer designs. Finally, the flexibility inherent in direct IF data conversion helps enable software-defined radio.
A linear, high-resolution, IF-generating DAC is an important component in direct IF data conversion. This DAC is an important building block in synthesizing a signal on the transmitter end, and is also an important building block in DS modulators that can directly digitize IF signals.
Multibit DACs, however, have limited linearity and resolution due to mismatch errors. Static mismatch errors occur when each DAC is driven by slightly different current sources, and dynamic timing errors occur when either the routing is unequal, or if the individual elements operate at different speeds. To correct for these errors, some type of electronic mismatch-correction needs to be implemented. Dynamic calibration, based on charge storage on the gate of the current-source transistors is a useful method for CMOS DACs, as shown in W. Schofield, D. Mercer. L. St. Onge, “A 16b 400 Ms/s DAC with <−80 dBc IMD to 300 MHz and <−160 dBm/Hz Noise Power Spectral Density”, ISSCC Digest of Technical Papers, 2003.
However, the highest-speed DACs use bipolar transistors. The calibration method in the above Schofield paper cannot be applied to bipolar implementations because the charge cannot be easily stored on the base of the transistor. Furthermore, calibration techniques only correct static mismatch errors, and hence some type of dynamic routing is necessary to correct timing errors.
Mismatch shapers are attractive for linearization because they can shape static and dynamic DAC mismatch errors away from a frequency of interest for a wide variety of DAC architectures, technologies, and types of mismatches. However, mismatch-shaping circuitry to date has been too slow to linearize direct-IF generating DACs. Due to the algorithmic complexity and resultant critical path delays, the fastest published mismatch shaped DACs are clocked at 60 MHz, as shown in Katelijn Vleugels, Shahriar Rabii, Bruce Wooley, “A 2.5-V Sigma-Delta Modulator for Broadband Communications Applications,” IEEE JSSC, vol. 36, no. 12, December 2001.
The faster mismatch shapers use averaging algorithms that are only suitable for generating signals at a small fraction of the sampling frequency, and as a result, the highest linearized IF produced was 2 MHz, as shown in the above Vleugels paper.
Bandpass mismatch shapers, which can theoretically be used to help directly generate signals closer to the Nyquist rate, have considerably higher system complexity and resultantly higher critical path delays. Thus, the highest IF directly generated from a bandpass mismatch shaper was 1.25 MHz, using a 5 MHz clock, as shown in L. Hernandez, A. Quesada, “Programmable Sine Wave Generator Employing a Mismatch-Shaping DAC,” ICECS Dig. Tech. Papers, 1998, pp. 135–138. Furthermore, none of these mismatch shapers have been tunable, and hence may not offer the needed flexibility for software-defined radio.